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VLSI Projects

S.NO 2017-2018 IEEE VLSI PROJECTS CODE YEAR
CMOS TECHNOLOGY
1 Temporarily Fine-Grained Sleep Technique for Near- and Sub threshold Parallel Architectures TVL1 2017
2 Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs TVL2 2017
3 Low-Complexity Multi-ternary Digit Multiplier Design in CNTFET Technology TVL3 2017
4 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression TVL4 2017
5 Design Considerations of Charge Pump for Antenna Switch Controller with SOI CMOS Technology TVL5 2017
6 An All-MOSFET Sub-1-V Voltage Reference With a −51-dB PSR up to 60 MHz TVL6 2017
7 A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS TVL7 2017
VLSI DESIGN
8 Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic TVL8 2017
9 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication TVL9 2017
10 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers TVL10 2017
11 Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing TVL11 2017
12 Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction TVL12 2017
13 Design and Analysis of Multiplier Using Approximate 15-4 Compressor TVL13 2017
14 Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique TVL14 2017
COMMUNICATION
15 Two Extra Column Trellis Min–Max Decoder Architecture for Non binary LDPC Codes TVL15 2017
16 Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm TVL16 2017
NoC
17 A Scalable Network-on-Chip Microprocessor with 2.5 D Integrated Memories and Accelerator TVL17 2017
18 Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links TVL18 2017
19 Secure and Dependable NoC-Connected Systems on an FPGA Chip TVL19 2017
CRYPTOGRAPHY
20 VLSI Implementation of a Cost-Efficient Micro Control Unit with an Asymmetric Encryption for Wireless Body Sensor Networks TVL20 2017
21 Cryptographically Secure Shield for Security IPs Protection TVL21 2017
22 Fault Space Transformation: A Generic Approach to Counter Differential Fault Analysis and Differential Fault Intensity Analysis on AES-like Block Ciphers TVL22 2017
23 A Custom Accelerator for Homomorphic Encryption Applications TVL23 2017
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