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VLSI Projects

1 Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators TVL1 2016
2 Hypergraph Based Minimum Arborescence Algorithm for the Optimization and Reoptimization of Multiple Constant Multiplications TVL2 2016
3 A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic TVL3 2016
4 Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication TVL4 2016
5 A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits TVL5 2016
6 Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design TVL6 2016
7 CORDIC II: A New Improved CORDIC Algorithm TVL7 2016
8 Low-Power Parallel Chien Search Architecture Using a Two-Step Approach TVL8 2016
9 Efficient Circuit for Parallel Bit Reversal TVL9 2016
10 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels TVL10 2016
11 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication TVL11 2016
12 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications TVL12 2016
13 Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems. TVL13 2016
14 Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures TVL14 2016
15 One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements TVL15 2016
16 Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis TVL16 2016
17 A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes TVL17 2016
18 A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM TVL18 2016
19 Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding TVL19 2016
20 Ultralow-Energy Variation-Aware Design: Adder Architecture Study TVL20 2016
21 SRAM-Based Unique Chip Identifier Techniques TVL21 2016
22 Implementing Minimum-Energy-Point Systems With Adaptive Logic TVL22 2016
23 On Efficient Retiming of Fixed-Point Circuits TVL23 2016
24 Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers TVL24 2016
25 Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip TVL25 2016
26 Concept, Design, and Implementation of Reconfigurable CORDIC TVL26 2016
27 A New CDMA Encoding/Decoding Method for on-Chip Communication Network TVL27 2016
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